1. Field of the Invention
The present invention relates to a pulse duty deterioration detection circuit for a pulse signal.
2. Description of the Related Art
Some of existing communication devices or the like are so designed as to operate based on an externally received clock as a reference. The clock receiving section of such a device receives a clock from outside, generates clocks of various frequencies based on that clock and distributes the clocks to the individual sections in the device. Therefore, the clock receiving section of the device has a duty monitoring capability which generates an alarm when an abnormality occurs in any of the clocks, and performs a process, such as inhibition of sending the abnormal clock to the associated section.
FIG. 1 shows a conventional circuit of this type which is disclosed in, for example, Japanese Patent Laid-Open No. 294632/1992. The circuit comprises an inverter 52 which inverts a to-be-monitored clock n50, a monostable multivibrator (hereinafter referred to as “MMV”) 51 which generates a reference pulse n51 synchronous with the rising of the to-be-monitored clock n50, an MMV 53 which generates a reference pulse n53 synchronous with the falling of the to-be-monitored clock n50, an FF (Flip-Flop) 54 which samples the reference pulse n51 at the rising of the output, n52, of the inverter 52, an FF 55 which samples the reference pulse n53 at the rising of the to-be-monitored clock n50 and an OR gate 56 which outputs the logical sum of an inverted output n54 of the FF 54 and inverted output n55 of the FF 55 as a duty monitor result n56.
With the structure, the to-be-monitored clock n50 is a trigger input to each of the MMVs 51 and 53, and the MMV 51 is triggered by the rising of the to-be-monitored clock n50 while the MMV 53 is triggered by the falling of the to-be-monitored clock n50. The output pulses n51 and n53 of the MMVs 51 and 53 are latched by the FFs 54 and 55, respectively. The latch timing of the FF 54 is the timing of the falling of the to-be-monitored clock n50 and the latch timing of the FF 55 is the timing of the rising of the to-be-monitored clock n50.
The inverted output n54 of the FF 54 and the inverted output n55 of the FF 55 are input to the OR gate 56 whose output n56 is the duty monitor result n56. The time constant, t, of the MMVs 51 and 53 is preset so as to be t=A×T where A is a reference duty ratio and T is the period of the to-be-monitored clock. Therefore, the output pulses n51 and n53 of the MMVs 51 and 53 are reference pulses which are respectively synchronous with the rising and falling of the to-be-monitored clock n50 and have the reference duty ratio. By sampling the levels of both output pulses at the rising and falling timings of the to-be-monitored clock n50 using the FFs 54 and 55, therefore, the inverted outputs n54 and n55 of the FFs 54 and 55 can have levels according to a change in the reference duty ratio of the to-be-monitored clock n50.
FIGS. 2 and 3 are time charts illustrating the operation of the circuit in FIG. 1, and FIG. 2 shows waveforms in case where the duty ratio of the to-be-monitored clock n50 is normal. In this case, the inverted outputs n54 and n55 of the FFs 54 and 55 both become “Low” levels and the output n56 of the OR gate 56 shows a “Low” level (normal). FIG. 3 shows waveforms in case where the duty ratio of the to-be-monitored clock n50 is greater than the reference duty ratio A. In this case, the inverted output n54 of the FF 54 is changed to a “High” level and the output n56 of the OR gate 56 shows a “High” level (abnormal).
The above-described prior art uses MMVs to monitor a variation in the phase of the edge portion of the to-be-monitored clock. The width of the output pulse can be changed by changing the value of a resistor to be added and the value of a capacitor.
Normally, the resistor and capacitor to be added are attached to the outside in consideration of an element error and the minimum values of the resistance of the resistor to be added and the capacitance which can guarantee the operation are about 1 kΩ and 60 pF, respectively. Therefore, the minimum pulse width set has an accuracy of about 60 ns, which is the set accuracy for the allowance range for the variation in the phase of the edge portion of the to-be-monitored clock. Apparently, the prior art has a shortcoming that the monitoring precision is deteriorated or monitoring cannot be performed at a frequency of over ten plus some MHz.
Further, the pulse width of an MMV has such a property as to have a great dependency on the supply voltage. The minimum value of the pulse width normally takes a value when supply voltage is about 5 V. Because the pulse width is inversely proportional to the supply voltage, however, the pulse width would be 100 ns or so when the supply voltage of the power supply of a low voltage as used in the recent portable telephones or the like becomes close to 3 V. This increases an error in the pulse width set, thus lowering the monitoring precision.